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» Designing hardware with dynamic memory abstraction
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GLOBECOM
2007
IEEE
15 years 4 months ago
A 10-Gbps High-Speed Single-Chip Network Intrusion Detection and Prevention System
Abstract—Network Intrusion Detection and Prevention Systems (NIDPSs) are vital in the fight against network intrusions. NIDPSs search for certain malicious content in network tr...
N. Sertac Artan, Rajdip Ghosh, Yanchuan Guo, H. Jo...
ASPDAC
2000
ACM
108views Hardware» more  ASPDAC 2000»
15 years 2 months ago
System-in-package (SIP): challenges and opportunities
Abstract - In this paper, we propose the concept of System-InPackage (SIP) as a generalization of System-On-Chip (SOC). System-In-Package overcomes formidable integration barriers ...
King L. Tai
CODES
2008
IEEE
15 years 4 months ago
Scratchpad allocation for concurrent embedded software
Software-controlled scratchpad memory is increasingly employed in embedded systems as it offers better timing predictability compared to caches. Previous scratchpad allocation alg...
Vivy Suhendra, Abhik Roychoudhury, Tulika Mitra
MICRO
2006
IEEE
103views Hardware» more  MICRO 2006»
15 years 3 months ago
NoSQ: Store-Load Communication without a Store Queue
This paper presents NoSQ (short for No Store Queue), a microarchitecture that performs store-load communication without a store queue and without executing stores in the outof-ord...
Tingting Sha, Milo M. K. Martin, Amir Roth
ISLPED
2010
ACM
202views Hardware» more  ISLPED 2010»
14 years 10 months ago
MODEST: a model for energy estimation under spatio-temporal variability
Estimation of static and dynamic energy of caches is critical for high-performance low-power designs. Commercial CAD tools performing energy estimation statically are not aware of...
Shrikanth Ganapathy, Ramon Canal, Antonio Gonz&aac...