453 search results - page 69 / 91 » Designing hardware with dynamic memory abstraction |
63
Voted
ACSD
2010
IEEE
14 years 7 months ago
2010
IEEE
Abstract--Clock gating and operand isolation are two techniques to reduce the power consumption in state-of-the-art hardware designs. Both approaches basically follow a two-step pr...
ISCA
2000
IEEE
15 years 2 months ago
2000
IEEE
Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardw...
87
Voted
ISRR
2001
Springer
15 years 2 months ago
2001
Springer
Abstract. This paper traces four years of evolution of the UNSW team in the RoboCup Sony legged robot league. The lessons learned in the creation of a competitive team are instruct...
72
Voted
ASPDAC
2009
ACM
15 years 4 months ago
2009
ACM
Abstract— Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32nm node. DPL decomposes...
ISCAS
2005
IEEE
15 years 3 months ago
2005
IEEE
Abstract — FPGAs offer excellent platform for System-onChips consisting of Intellectual Property (IP) blocks. The problem is that IP blocks and their interconnections are often F...