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TVLSI
2011
265views more  TVLSI 2011»
14 years 4 months ago
Decoding-Aware Compression of FPGA Bitstreams
Abstract—Bitstream compression is important in reconfigurable system design since it reduces the bitstream size and the memory requirement. It also improves the communication ba...
Xiaoke Qin, Chetan Muthry, Prabhat Mishra
MATA
2004
Springer
199views Communications» more  MATA 2004»
15 years 3 months ago
Configuration Management for Networked Reconfigurable Embedded Devices
Distribution of product updates to embedded devices can increase product lifetimes for consumers and boost revenues for vendors. Dynamic provisioning of application solutions to e...
Timothy O'Sullivan, Richard Studdert
84
Voted
MICRO
2010
IEEE
119views Hardware» more  MICRO 2010»
14 years 4 months ago
Task Superscalar: An Out-of-Order Task Pipeline
We present Task Superscalar, an abstraction of instruction-level out-of-order pipeline that operates at the tasklevel. Like ILP pipelines, which uncover parallelism in a sequential...
Yoav Etsion, Felipe Cabarcas, Alejandro Rico, Alex...
DATE
1998
IEEE
153views Hardware» more  DATE 1998»
15 years 1 months ago
An Energy-Conscious Exploration Methodology for Reconfigurable DSPs
As the "system-on-a-chip" concept is rapidly becoming a reality, time-to-market and product complexity push the reuse of complex macromodules. Circuits combining a varie...
Jan M. Rabaey, Marlene Wan
ISPASS
2010
IEEE
15 years 4 months ago
Synthesizing memory-level parallelism aware miniature clones for SPEC CPU2006 and ImplantBench workloads
Abstract—We generate and provide miniature synthetic benchmark clones for modern workloads to solve two pre-silicon design challenges, namely: 1) huge simulation time (weeks to m...
Karthik Ganesan, Jungho Jo, Lizy K. John