103 search results - page 14 / 21 » Designing multi-socket systems using silicon photonics |
IPPS
2000
IEEE
15 years 4 months ago
2000
IEEE
As processor speeds rapidly approach the Giga-Hertz regime, the disparity between process time and memory access time plays an increasing role in the overall limitation of processo...
DAC
2005
ACM
16 years 21 days ago
2005
ACM
Device and interconnect fabrics at the nanoscale will have a density of defects and susceptibility to transient faults far exceeding those of current silicon technologies. In this...
DAC
2005
ACM
15 years 1 months ago
2005
ACM
Parallelism in processor architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. In this paper...
CODES
2006
IEEE
15 years 5 months ago
2006
IEEE
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...
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TVLSI
2010
14 years 6 months ago
2010
By storing more than one bit in each memory cell, multi-level per cell (MLC) NAND flash memories are dominating global flash memory market due to their appealing storage density ad...