1226 search results - page 130 / 246 » Designing systems-on-chip using cores |
113
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DAC
2001
ACM
16 years 2 months ago
2001
ACM
This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-ph...
130
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HEURISTICS
2000
15 years 1 months ago
2000
Planning and designing the next generation of IP router or switched broadband networks seems a daunting challenge considering the many complex, interacting factors affecting the p...
114
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JVA
2006
IEEE
15 years 7 months ago
2006
IEEE
In this paper, we will introduce to describe learning resources by using ontology model based on metadata of learning standard as Sharable Content Object Reference Model (SCORM) a...
109
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APLAS
2007
ACM
15 years 5 months ago
2007
ACM
We propose a series of type systems for the information-flow security of assembly code. These systems extend previous work TALC with some timing annotations and associated judgment...
123
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ISQED
2010
IEEE
14 years 11 months ago
2010
IEEE
This paper studies multi-core clock distribution using active deskewing methods. We propose an efficient methodology that uses Verilog-A to model PLLs, clock trees and power suppl...