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» Designing systems-on-chip using cores
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HPDC
2012
IEEE
13 years 3 months ago
vSlicer: latency-aware virtual machine scheduling via differentiated-frequency CPU slicing
Recent advances in virtualization technologies have made it feasible to host multiple virtual machines (VMs) in the same physical host and even the same CPU core, with fair share ...
Cong Xu, Sahan Gamage, Pawan N. Rao, Ardalan Kanga...
115
Voted
CODES
2007
IEEE
15 years 7 months ago
Performance modeling for early analysis of multi-core systems
Performance analysis of microprocessors is a critical step in defining the microarchitecture, prior to register-transfer-level (RTL) design. In complex chip multiprocessor systems...
Reinaldo A. Bergamaschi, Indira Nair, Gero Dittman...
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
15 years 6 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
DAC
2009
ACM
16 years 2 months ago
Efficient program scheduling for heterogeneous multi-core processors
Heterogeneous multicore processors promise high execution efficiency under diverse workloads, and program scheduling is critical in exploiting this efficiency. This paper present...
Jian Chen, Lizy Kurian John
103
Voted
PERCOM
2008
ACM
16 years 1 months ago
Data-centric middleware for context-aware pervasive computing
The complexity of developing and deploying context-aware pervasive-computing applications calls for distributed software infrastructures that assist applications to collect, aggre...
Guanling Chen, Ming Li, David Kotz