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» Designing systems-on-chip using cores
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ISCA
2007
IEEE
182views Hardware» more  ISCA 2007»
15 years 7 months ago
Configurable isolation: building high availability systems with commodity multi-core processors
High availability is an increasingly important requirement for enterprise systems, often valued more than performance. Systems designed for high availability typically use redunda...
Nidhi Aggarwal, Parthasarathy Ranganathan, Norman ...
RSP
2007
IEEE
143views Control Systems» more  RSP 2007»
15 years 7 months ago
Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs
Multiprocessor Systems-on-Chip (MPSoCs) is a trend in VLSI design, since they minimize the “design crisis” (gap between silicon technology and actual SoC design capacity) and ...
Ewerson Carvalho, Ney Calazans, Fernando Moraes
FDL
2006
IEEE
15 years 7 months ago
MCF: A Metamodeling-based Visual Component Composition Framework
Reusing IP-cores to construct system models facilitated by automated generation of glue-logic, and automated composability checks can help designers to create efficient simulation...
Deepak Mathaikutty, Sandeep K. Shukla
SIGCOMM
2005
ACM
15 years 6 months ago
Declarative routing: extensible routing with declarative queries
The Internet’s core routing infrastructure, while arguably robust and efficient, has proven to be difficult to evolve to accommodate the needs of new applications. Prior researc...
Boon Thau Loo, Joseph M. Hellerstein, Ion Stoica, ...

Publication
351views
17 years 1 months ago
Synthesizable High Level Hardware Descriptions
Modern hardware description languages support code-generation constructs like generate/endgenerate in Verilog. These constructs are intended to describe regular or parameterized ha...
Jennifer Gillenwater, Gregory Malecha, Cherif Sala...