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» Designing systems-on-chip using cores
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ISCA
2010
IEEE
239views Hardware» more  ISCA 2010»
15 years 6 months ago
Sentry: light-weight auxiliary memory access control
Light-weight, flexible access control, which allows software to regulate reads and writes to any granularity of memory region, can help improve the reliability of today’s multi...
Arrvindh Shriraman, Sandhya Dwarkadas
CAL
2007
15 years 1 months ago
Logic-Based Distributed Routing for NoCs
—The design of scalable and reliable interconnection networks for multicore chips (NoCs) introduces new design constraints like power consumption, area, and ultra low latencies. ...
José Flich, José Duato
HIPC
2009
Springer
14 years 11 months ago
Fast checkpointing by Write Aggregation with Dynamic Buffer and Interleaving on multicore architecture
Large scale compute clusters continue to grow to ever-increasing proportions. However, as clusters and applications continue to grow, the Mean Time Between Failures (MTBF) has redu...
Xiangyong Ouyang, Karthik Gopalakrishnan, Tejus Ga...
DAC
2008
ACM
16 years 2 months ago
On reliable modular testing with vulnerable test access mechanisms
In modular testing of system-on-a-chip (SoC), test access mechanisms (TAMs) are used to transport test data between the input/output pins of the SoC and the cores under test. Prio...
Lin Huang, Feng Yuan, Qiang Xu
SIGMOD
2009
ACM
214views Database» more  SIGMOD 2009»
16 years 1 months ago
DDE: from dewey to a fully dynamic XML labeling scheme
Labeling schemes lie at the core of query processing for many XML database management systems. Designing labeling schemes for dynamic XML documents is an important problem that ha...
Liang Xu, Tok Wang Ling, Huayu Wu, Zhifeng Bao