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» Designing systems-on-chip using cores
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FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
15 years 1 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
CLOUD
2010
ACM
15 years 6 months ago
Stateful bulk processing for incremental analytics
This work addresses the need for stateful dataflow programs that can rapidly sift through huge, evolving data sets. These data-intensive applications perform complex multi-step c...
Dionysios Logothetis, Christopher Olston, Benjamin...
SIGSOFT
2009
ACM
16 years 2 months ago
DebugAdvisor: a recommender system for debugging
In large software development projects, when a programmer is assigned a bug to fix, she typically spends a lot of time searching (in an ad-hoc manner) for instances from the past ...
B. Ashok, Joseph M. Joy, Hongkang Liang, Sriram K....
HPCA
2007
IEEE
16 years 1 months ago
A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On t...
Ricardo Fernández Pascual, José M. G...
POPL
2008
ACM
16 years 1 months ago
Boomerang: resourceful lenses for string data
A lens is a bidirectional program. When read from left to right, it denotes an ordinary function that maps inputs to outputs. When read from right to left, it denotes an "upd...
Aaron Bohannon, J. Nathan Foster, Benjamin C. Pier...