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» Designing systems-on-chip using cores
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NOSSDAV
2004
Springer
15 years 6 months ago
Reduced state fair queuing for edge and core routers
Despite many years of research, fair queuing still faces a number of implementation challenges in high speed routers. In particular, in spite of proposals such as DiffServ, the st...
Ramana Rao Kompella, George Varghese
ISCA
2010
IEEE
176views Hardware» more  ISCA 2010»
15 years 5 months ago
Forwardflow: a scalable core for power-constrained CMPs
Chip Multiprocessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased coreper-socket c...
Dan Gibson, David A. Wood
ICDE
2007
IEEE
170views Database» more  ICDE 2007»
15 years 5 months ago
A UML Profile for Core Components and their Transformation to XSD
In business-to-business e-commerce, traditional electronic data interchange (EDI) approaches such as UN/EDIFACT have been superseded by approaches like web services and ebXML. Nev...
Christian Huemer, Philipp Liegl
ISPDC
2010
IEEE
14 years 11 months ago
Resource-Aware Compiler Prefetching for Many-Cores
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
George C. Caragea, Alexandros Tzannes, Fuat Keceli...
OSDI
1996
ACM
15 years 2 months ago
Automatic Compiler-Inserted I/O Prefetching for Out-of-Core Applications
Current operating systems offer poor performance when a numeric application's working set does not fit in main memory. As a result, programmers who wish to solve "out-of...
Todd C. Mowry, Angela K. Demke, Orran Krieger