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MICRO
2002
IEEE
122views Hardware» more  MICRO 2002»
15 years 6 months ago
Microarchitectural denial of service: insuring microarchitectural fairness
Simultaneous multithreading seeks to improve the aggregate computation bandwidth of a processor core by sharing resources such as functional units, caches, TLB and so on. To date,...
Dirk Grunwald, Soraya Ghiasi
ITC
2000
IEEE
74views Hardware» more  ITC 2000»
15 years 5 months ago
A good excuse for reuse: "open" TAP controller design
In this paper we present a design for IEEE 1149.1 Test Access Port (TAP)controllers that is based on a practical reuse methodology. While the basic use and core functionality of T...
David B. Lavo
ICCSA
2005
Springer
15 years 6 months ago
A Systematic Process to Design Product Line Architecture
Product Line Engineering is being accepted as a representative software reuse methodology by using core assets and product line architecture is known as a key element of core asset...
Soo Dong Kim, Soo Ho Chang, Hyun Jung La
IEEEPACT
2008
IEEE
15 years 7 months ago
Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor
Moore’s Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneo...
Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aa...
FPL
2010
Springer
155views Hardware» more  FPL 2010»
14 years 11 months ago
Design and Implementation of Real-Time Transactional Memory
Transactional memory is a promising, optimistic synchronization mechanism for chip-multiprocessor systems. The simplicity of atomic sections, instead of using explicit locks, is al...
Martin Schoeberl, Peter Hilber