This paper presents a mechanism for the separation of control and data flow in NoC-based SoCs consisting of multiple heterogeneous reconfigurable IP cores. This mechanism enables ...
This paper introduces SCIVE, a Simulation Core for Intelligent Virtual Environments. SCIVE provides a Knowledge Representation Layer (KRL) as a central organizing struc...
With technology advances, the number of cores integrated on a chip and their speed of operation is increasing. This, in turn is leading to a significant increase in chip temperat...
Srinivasan Murali, Almir Mutapcic, David Atienza, ...
The IPSI XQuery Demonstrator (IPSI-XQ) implements the XQuery surface syntax, its mapping to the XQuery Core Language, and the static and dynamic semantics of XQuery Core "by t...
Heteregenous multiprocessor SoCs are becoming a reality, largely due to the abundance of transistors, intellectual property cores and powerful design tools. In this project, we ex...