1226 search results - page 44 / 246 » Designing systems-on-chip using cores |
DATE
2006
IEEE
15 years 7 months ago
2006
IEEE
This paper presents a wrapper and test access mechanism design for multi-clock domain SoCs that consists of cores with different clock frequencies during test. We also propose a t...
DFT
2007
IEEE
15 years 7 months ago
2007
IEEE
In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemen...
100
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MICRO
1999
IEEE
15 years 5 months ago
1999
IEEE
Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that ...
108
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DATE
2008
IEEE
15 years 7 months ago
2008
IEEE
Modern digital signal processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many appl...
298
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EGPGV
2011
Springer
14 years 4 months ago
2011
Springer
We present a state of the art read-only distributed shared memory (DSM) ray tracer capable of fully utilizing modern cluster hardware to render massive out-of-core polygonal model...