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» Designing systems-on-chip using cores
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ARC
2009
Springer
165views Hardware» more  ARC 2009»
15 years 8 months ago
Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform
Abstract. Most hardware/software codesigns of Elliptic Curve Cryptography only have one central control unit, typically a 32 bit or 8 bit processor core. With the ability of integr...
Xu Guo, Patrick Schaumont
MICRO
2008
IEEE
137views Hardware» more  MICRO 2008»
15 years 7 months ago
Tradeoffs in designing accelerator architectures for visual computing
Visualization, interaction, and simulation (VIS) constitute a class of applications that is growing in importance. This class includes applications such as graphics rendering, vid...
Aqeel Mahesri, Daniel R. Johnson, Neal C. Crago, S...
CHES
2011
Springer
240views Cryptology» more  CHES 2011»
14 years 1 months ago
Lightweight and Secure PUF Key Storage Using Limits of Machine Learning
A lightweight and secure key storage scheme using silicon Physical Unclonable Functions (PUFs) is described. To derive stable PUF bits from chip manufacturing variations, a lightwe...
Meng-Day (Mandel) Yu, David M'Raïhi, Richard ...
MTDT
2003
IEEE
105views Hardware» more  MTDT 2003»
15 years 6 months ago
A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories
Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be ...
Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu L...
MICRO
2010
IEEE
215views Hardware» more  MICRO 2010»
14 years 11 months ago
A Task-Centric Memory Model for Scalable Accelerator Architectures
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
John H. Kelm, Daniel R. Johnson, Steven S. Lumetta...