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» Designing systems-on-chip using cores
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ASYNC
2004
IEEE
102views Hardware» more  ASYNC 2004»
15 years 5 months ago
Non-Uniform Access Asynchronous Register Files
Register files of microprocessors have often been cited as performance bottlenecks and significant consumers of energy. The robust and modular nature of quasi-delay insensitive (Q...
David Fang, Rajit Manohar
ECIS
2003
15 years 2 months ago
Acting out the future: a process for envisionment
It is difficult to design innovative information and communication technologies to meet needs that will emerge from future interactions between users, technologies and their situa...
Jennie Carroll, Daniel Tobin
DATE
2009
IEEE
178views Hardware» more  DATE 2009»
15 years 8 months ago
ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration
As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constr...
Andrew B. Kahng, Bin Li, Li-Shiuan Peh, Kambiz Sam...
DAC
2002
ACM
16 years 2 months ago
Embedded software-based self-testing for SoC design
At-speed testing of high-speed circuits is becoming increasingly difficult with external testers due to the growing gap between design and tester performance, growing cost of high...
Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li...
ISCA
2010
IEEE
240views Hardware» more  ISCA 2010»
15 years 6 months ago
Modeling critical sections in Amdahl's law and its implications for multicore design
This paper presents a fundamental law for parallel performance: it shows that parallel performance is not only limited by sequential code (as suggested by Amdahl’s law) but is a...
Stijn Eyerman, Lieven Eeckhout