Sciweavers

1226 search results - page 75 / 246
» Designing systems-on-chip using cores
Sort
View
FPL
2009
Springer
145views Hardware» more  FPL 2009»
15 years 6 months ago
Run-time Partial Reconfiguration speed investigation and architectural design space exploration
Run-time Partial Reconfiguration (PR) speed is significant in applications especially when fast IP core switching is required. In this paper, we propose to use Direct Memory Acce...
Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsc...
ASAP
2007
IEEE
97views Hardware» more  ASAP 2007»
15 years 3 months ago
FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers
This paper presents an optimized design approach of two’s complement large-size squarers using embedded multipliers in FPGAs. The realization is based on BaughWooley’s algorit...
Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, ...
ISSS
2002
IEEE
151views Hardware» more  ISSS 2002»
15 years 6 months ago
Tuning of Loop Cache Architectures to Programs in Embedded System Design
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
Frank Vahid, Susan Cotterell
IASSE
2004
15 years 2 months ago
System Evolution through Design Information Evolution: a Case Study
This paper describes how design information, in our case UML specifications, can be used to evolve a software system and validate the consistency of such an evolution. This work c...
Walter Cazzola, Ahmed Ghoneim, Gunter Saake
ICEGOV
2009
ACM
14 years 11 months ago
Design of a web-based tendering system for e-government procurement
Procurement for e-Government is an important part of activities which are similar to the nature of B2B. That is usually characterized by bulk volumes with complex variables, burea...
Simon Fong, Zhuang Yan