1226 search results - page 86 / 246 » Designing systems-on-chip using cores |
100
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DSD
2005
IEEE
15 years 7 months ago
2005
IEEE
The increasing amount of test data needed to test SOC (System-on-Chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the...
117
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ARCS
2009
Springer
15 years 8 months ago
2009
Springer
The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...
ASPDAC
2004
ACM
15 years 6 months ago
2004
ACM
: A single-chip 512-point FFT processor is presented. This processor is based on the cached-memory architecture (CMA) with the resource-saving multidatapath radix-23 computation el...
109
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CCR
2005
15 years 1 months ago
2005
This article describes how control theory has been used to address the question of how to size the buffers in core Internet routers. Control theory aims to predict whether the net...
125
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IEEEIAS
2009
IEEE
14 years 11 months ago
2009
IEEE
In this paper, we propose a framework to develop highperformance system accelerator hardware and the corresponding software at system-level. This framework is designed by integrat...