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ICCD
2007
IEEE
105views Hardware» more  ICCD 2007»
16 years 3 months ago
Exploring the interplay of yield, area, and performance in processor caches
The deployment of future deep submicron technology calls for a careful review of existing cache organizations and design practices in terms of yield and performance. This paper pr...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
PUC
2006
94views more  PUC 2006»
15 years 6 months ago
Appliances for whom? Considering place
We discuss homes as potential settings for the products of appliance design. We catalog the large international and regional differences. We look at differences in terms of infrast...
Jennifer Ann Rode
DATE
2007
IEEE
100views Hardware» more  DATE 2007»
16 years 15 days ago
Life begins at 65: unless you are mixed signal?
The old school of analog designers, exemplified by pioneer Bob Pease, is becoming an extinct species. But the demand for analog/mixed-signal IP blocks has never been greater, espe...
Reimund Wittmann, Massimo Vanzi, Hans-Joachim Wass...
148
Voted
CSCWD
2008
Springer
15 years 8 months ago
Distributed workflows for multi-physics applications in aeronautics
The industry requires innovative technologies to support the numeric design and simulation of manufactured products in order to reduce time to market delays and improve the perfor...
T. Nguyen, J.-A. Desideri, J. Periaux
170
Voted
ARCS
2006
Springer
15 years 10 months ago
Do Trace Cache, Value Prediction and Prefetching Improve SMT Throughput?
While trace cache, value prediction, and prefetching have been shown to be effective in the single-threaded superscalar, there has been no analysis of these techniques in a Simulta...
Chen-Yong Cher, Il Park, T. N. Vijaykumar