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78
Voted
GLVLSI
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as c...
72
Voted
MICRO
2006
IEEE
15 years 3 months ago
2006
IEEE
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identi...
TAICPART
2006
IEEE
15 years 3 months ago
2006
IEEE
One of the key roles of any information system is to enforce the business rules and policies set by the owning organisation. As for any important functionality, it is necessary to...
ASPLOS
2006
ACM
15 years 3 months ago
2006
ACM
For transactional memory (TM) to achieve widespread acceptance, transactions should not be limited to the physical resources of any specific hardware implementation. TM systems s...
CASES
2006
ACM
15 years 3 months ago
2006
ACM
Virtual caches are employed as L1 caches of both high performance and embedded processors to meet their short latency requirements. However, they also introduce the synonym proble...