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DATE
2010
IEEE
162views Hardware» more  DATE 2010»
15 years 4 months ago
Error resilience of intra-die and inter-die communication with 3D spidergon STNoC
: Scaling down in very deep submicron (VDSM) technologies increases the delay, power consumption of on-chip interconnects, while the reliability and yield decrease. In high perform...
Vladimir Pasca, Lorena Anghel, Claudia Rusu, Ricca...
ATAL
1999
Springer
15 years 3 months ago
A Planning Component for RETSINA Agents
In the RETSINA multi-agent system, each agent is provided with an internal planning component—the RETSINA planner. Each agent, using its internal planner, formulates detailed pla...
Massimo Paolucci, Onn Shehory, Katia P. Sycara, Di...
ICSE
2000
IEEE-ACM
15 years 2 months ago
Generating statechart designs from scenarios
This paper presents an algorithm for automatically generating UML statecharts from a collection of UML sequence diagrams. Computer support for this transition between requirements...
Jon Whittle, Johann Schumann
STTT
2010
97views more  STTT 2010»
14 years 9 months ago
Distributed dynamic partial order reduction
Abstract. Runtime (dynamic) model checking is a promising verification methodology for real-world threaded software because of its many features, the prominent ones being: (i) it ...
Yu Yang, Xiaofang Chen, Ganesh Gopalakrishnan, Rob...
NFM
2011
223views Formal Methods» more  NFM 2011»
14 years 6 months ago
Generating Data Race Witnesses by an SMT-Based Analysis
Abstract. Data race is one of the most dangerous errors in multithreaded programming, and despite intensive studies, it remains a notorious cause of failures in concurrent systems....
Mahmoud Said, Chao Wang, Zijiang Yang, Karem Sakal...