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ASAP
2005
IEEE
133views Hardware» more  ASAP 2005»
15 years 12 months ago
Speedups from Partitioning Critical Software Parts to Coarse-Grain Reconfigurable Hardware
In this paper, we propose a hardware/software partitioning method for improving applications’ performance in embedded systems. Critical software parts are accelerated on hardwar...
Michalis D. Galanis, Grigoris Dimitroulakos, Costa...
DATE
2005
IEEE
96views Hardware» more  DATE 2005»
15 years 12 months ago
DVS for On-Chip Bus Designs Based on Timing Error Correction
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching patter...
Himanshu Kaul, Dennis Sylvester, David Blaauw, Tre...
DATE
2005
IEEE
115views Hardware» more  DATE 2005»
15 years 12 months ago
Functional Coverage Driven Test Generation for Validation of Pipelined Processors
Functional verification of microprocessors is one of the most complex and expensive tasks in the current system-on-chip design process. A significant bottleneck in the validatio...
Prabhat Mishra, Nikil D. Dutt
DATE
2005
IEEE
135views Hardware» more  DATE 2005»
15 years 12 months ago
Compositional Memory Systems for Multimedia Communicating Tasks
Conventional cache models are not suited for real-time parallel processing because tasks may flush each other’s data out of the cache in an unpredictable manner. In this way th...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
EH
2005
IEEE
171views Hardware» more  EH 2005»
15 years 12 months ago
Implementation Results for a Fault-Tolerant Multicellular Architecture Inspired by Endocrine Communication
The hybrid redundancy structure found at the cellular level of higher animals provides complex organism with the three key features of a reliability-engineered system: fault toler...
Andrew J. Greensted, Andy M. Tyrrell
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