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» Deterministic Logic BIST for Transition Fault Testing
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ITC
2003
IEEE
134views Hardware» more  ITC 2003»
15 years 2 months ago
Effectiveness Improvement of ECR Tests
Energy Consumption Ratio (ECR) test, a current-based test, has shown its ability to reduce the impact of process variations and detect hard-to-detect faults. The effectiveness of ...
Wanli Jiang, Erik Peterson, Bob Robotka
TCAD
2002
134views more  TCAD 2002»
14 years 9 months ago
Testing and diagnosis of interconnect faults in cluster-based FPGA architectures
As IC densities are increasing, cluster-based FPGA architectures are becoming the architecture of choice for major FPGA manufacturers. A cluster-based architecture is one in which...
Ian G. Harris, Russell Tessier
ITC
2003
IEEE
149views Hardware» more  ITC 2003»
15 years 2 months ago
On Reducing Aliasing Effects and Improving Diagnosis of Logic BIST Failures
Diagnosing failing vectors in a Built-In Self Test (BIST) environment is a difficult task because of the highly compressed signature coming out of the Multiple Input Shift Regist...
Ramesh C. Tekumalla
ICCAD
2000
IEEE
124views Hardware» more  ICCAD 2000»
15 years 2 months ago
Deterministic Test Pattern Generation Techniques for Sequential Circuits
This paper presents new test generation techniques for improving the average-case performance of the iterative logic array based deterministic sequential circuit test generation a...
Ilker Hamzaoglu, Janak H. Patel
DFT
2002
IEEE
121views VLSI» more  DFT 2002»
15 years 2 months ago
Testing Digital Circuits with Constraints
Many digital circuits have constraints on the logic values a set of signal lines can have. In this paper, we present two new techniques for detecting the illegal combinations of l...
Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McC...