73 search results - page 2 / 15 » Deterministic Logic BIST for Transition Fault Testing |
ITC
1996
IEEE
15 years 1 months ago
1996
IEEE
This paper presents a low-overhead scheme for built-in self-test of circuits with scan. Complete (100%) fault coverage is obtained without modifying the function logic and without...
ITC
1999
IEEE
15 years 1 months ago
1999
IEEE
This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200K t...
VTS
2003
IEEE
15 years 2 months ago
2003
IEEE
Reseeding is used to improve fault coverage in pseudo-random testing. Most of the work done on reseeding is based on storing the seeds in an external tester. Besides its high cost...
GLVLSI
2005
IEEE
15 years 3 months ago
2005
IEEE
We develop a novel on-line built-in self-test (BIST) technique for testing FPGAs that has a very high diagnosability even in presence of clustered faults, a fault pattern for whic...
VTS
2000
IEEE
15 years 2 months ago
2000
IEEE
1 At-speed testing is becoming increasingly difficult with external testers as the speed of microprocessors approaches the GHz range. One solution to this problem is built-in self-...