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SIPS
2007
IEEE
15 years 9 months ago
An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding
Stochastic decoding is a new alternative method for low complexity decoding of error-correcting codes. This paper presents the first hardware architecture for stochastic decoding...
Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gros...
SWAT
1994
Springer
120views Algorithms» more  SWAT 1994»
15 years 6 months ago
Parallel Dynamic Lowest Common Ancestors
This paper gives a CREW PRAM algorithm for the problem of finding lowest common ancestors in a forest under the insertion of leaves and roots and the deletion of leaves. For a fore...
Erik Schenk
138
Voted
PATMOS
2000
Springer
15 years 6 months ago
Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications
Exploitation of data re-use in combination with the use of custom memory hierarchy that exploits the temporal locality of data accesses may introduce significant power savings, esp...
Dimitrios Soudris, Nikolaos D. Zervas, Antonios Ar...
COLOGNETWENTE
2008
15 years 4 months ago
Special Cases of Online Parallel Job Scheduling
In this paper we consider the online scheduling of jobs, which require processing on a number of machines simultaneously. These jobs are presented to a decision maker one by one, ...
Johann Hurink, Jacob Jan Paulus
ESANN
2008
15 years 4 months ago
Parallel asynchronous neighborhood mechanism for WTM Kohonen network implemented in CMOS technology
In this paper we present an original neighborhood mechanism for WTM self-organizing Kohonen map implemented in CMOS 0.18 m process. Proposed mechanism is an asynchronous circuit an...
Marta Kolasa, Rafal Dlugosz