5171 search results - page 459 / 1035 » Deterministic Parallel Processing |
149
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CONCUR
2008
Springer
15 years 6 months ago
2008
Springer
We present a framework that combines ideas from spatial logics and Igarashi and Kobayashi's behavioural type systems, drawing benefits from both. In our approach, type systems...
150
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EUROPAR
2008
Springer
15 years 6 months ago
2008
Springer
Cache affinity between a process and a processor is observed when the processor cache has accumulated some amount of the process state, i.e., data or instructions. Cache affinity i...
158
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IFIP12
2007
15 years 5 months ago
2007
In this paper an efficient architecture for natural language processing is presented, implemented in hardware using FPGAs (Field Programmable Gate Arrays). The system can receive s...
121
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WSC
2004
15 years 5 months ago
2004
In standard optimistic parallel event simulation, no restriction exists on the maximum lag in simulation time between the fastest and slowest logical processes (LPs). Overoptimist...
161
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CDES
2009
15 years 5 months ago
2009
Recent developments in processing devices such as graphical processing units and multi-core systems offer opportunities to make use of parallel techniques at the chip level to obt...