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FPL
2006
Springer
105views Hardware» more  FPL 2006»
15 years 10 months ago
A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node. The processor has an arch...
K. Van Renterghem, Dieter Verhulst, S. Verschuere,...
FPGA
2000
ACM
128views FPGA» more  FPGA 2000»
15 years 10 months ago
Factoring large numbers with programmable hardware
The fastest known algorithms for factoring large numbers share a core sieving technique. The sieving cores find numbers that are completely factored over a prime base set raised t...
Hea Joung Kim, William H. Mangione-Smith
PODC
1995
ACM
15 years 10 months ago
A Framework for Protocol Composition in Horus
The Horus system supports a communication architecture ats protocols as instances of an abstract data type. This approach encourages developers to partition complex protocols into...
Robbert van Renesse, Kenneth P. Birman, Roy Friedm...
HLPPP
1991
15 years 10 months ago
Reasoning About Synchronic Groups
Swarm is a computational model which extends the UNITY model in three important ways: (1) UNITY’s fixed set of variables is replaced by an unbounded set of tuples which are add...
Gruia-Catalin Roman, H. Conrad Cunningham
CW
2005
IEEE
15 years 8 months ago
Using a Floating Origin to Improve Fidelity and Performance of Large, Distributed Virtual Worlds
Large Virtual Worlds (VWs) are increasingly common in the computer graphics areas of simulation, games, geospatial or scientific visualisation. In such VWs, simulated motion of th...
Chris Thorne