115 search results - page 14 / 23 » Deterministic Test Pattern Generation Techniques for Sequent... |
DFT
2003
IEEE
15 years 5 months ago
2003
IEEE
1 This paper presents a solution to the test time minimization problem for core-based systems that contain sequential cores with STUMPS architecture. We assume a hybrid BIST approa...
DELTA
2008
IEEE
15 years 6 months ago
2008
IEEE
Scan is a widely used design-for-testability technique to improve test and diagnosis quality, however, scan chain failures account for almost 50% of chip failures. In this paper, ...
106
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DAC
2003
ACM
15 years 4 months ago
2003
ACM
To improve the system performance, designs with multiple clocks have become more and more popular. In this paper, several novel test generation procedures are proposed to utilize ...
111
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EVOW
2001
Springer
15 years 4 months ago
2001
Springer
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
FPL
2004
Springer
15 years 5 months ago
2004
Springer
Abstract. We present an evaluation of accelerating fault simulation by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is fre...