115 search results - page 17 / 23 » Deterministic Test Pattern Generation Techniques for Sequent... |
VTS
2002
IEEE
15 years 2 months ago
2002
IEEE
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
DSD
2005
IEEE
14 years 11 months ago
2005
IEEE
Several methods improving the fault coverage in mixed-mode BIST are presented in this paper. The test is divided into two phases: the pseudo-random and deterministic. Maximum of f...
81
Voted
VLSID
2005
IEEE
15 years 10 months ago
2005
IEEE
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
82
Voted
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
Abstract-Multi-detect (N-detect) testing suffers from the drawback that its test length grows linearly with N. We present a new method to generate compact test sets that provide hi...
84
Voted
DAC
1999
ACM
15 years 1 months ago
1999
ACM
As the sizes of general and special purpose processors increase rapidly, generating high quality manufacturing tests which can be run at native speeds is becoming a serious proble...