115 search results - page 23 / 23 » Deterministic Test Pattern Generation Techniques for Sequent... |
ET
2010
13 years 4 months ago
2010
Abstract As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to...
ISCAS
2006
IEEE
14 years 8 days ago
2006
IEEE
— All-solution Boolean satisfiability (SAT) solvers are engines employed to find all the possible solutions to a SAT problem. Their applications are found throughout the EDA in...
ICCAD
2002
IEEE
13 years 11 months ago
2002
IEEE
The ultimate goal of logic synthesis is to explore implementation flexibility toward meeting design targets, such as area, power, and delay. Traditionally, such flexibility is exp...
ICDCS
2008
IEEE
14 years 21 days ago
2008
IEEE
The multi-level storage architecture has been widely adopted in servers and data centers. However, while prefetching has been shown as a crucial technique to exploit the sequentia...
ICCAD
1999
IEEE
13 years 10 months ago
1999
IEEE
In this paper we present new methods for fast justification and propagation in the implication graph (IG) which is the core data structure of our SAT based implication engine. As ...