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MICRO
2010
IEEE
215views Hardware» more  MICRO 2010»
14 years 12 months ago
A Task-Centric Memory Model for Scalable Accelerator Architectures
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
John H. Kelm, Daniel R. Johnson, Steven S. Lumetta...
NAACL
2010
14 years 11 months ago
Predicting Human-Targeted Translation Edit Rate via Untrained Human Annotators
In the field of machine translation, automatic metrics have proven quite valuable in system development for tracking progress and measuring the impact of incremental changes. Howe...
Omar Zaidan, Chris Callison-Burch
NAACL
2010
14 years 11 months ago
Extracting Parallel Sentences from Comparable Corpora using Document Level Alignment
The quality of a statistical machine translation (SMT) system is heavily dependent upon the amount of parallel sentences used in training. In recent years, there have been several...
Jason R. Smith, Chris Quirk, Kristina Toutanova
SIGMOD
2009
ACM
157views Database» more  SIGMOD 2009»
16 years 1 months ago
FPGA: what's in it for a database?
While there seems to be a general agreement that next years' systems will include many processing cores, it is often overlooked that these systems will also include an increa...
Jens Teubner, René Müller
DAC
2002
ACM
16 years 2 months ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...