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ASPDAC
2009
ACM
153views Hardware» more  ASPDAC 2009»
14 years 9 months ago
A 3D prototyping chip based on a wafer-level stacking technology
We have developed a new 3-dimensional stacking technology using wafer-to-wafer stacked method and evaluated the connectivity between TSV and micro-bump. The prototype 3-layer stac...
Nobuaki Miyakawa
COLING
2010
14 years 6 months ago
A Minimum Error Weighting Combination Strategy for Chinese Semantic Role Labeling
Many Semantic Role Labeling (SRL) combination strategies have been proposed and tested on English SRL task. But little is known about how much Chinese SRL can benefit from system ...
Tao Zhuang, Chengqing Zong
KBSE
2006
IEEE
15 years 5 months ago
Mining Aspects from Version History
Aspect mining identifies cross-cutting concerns in a program to help migrating it to an aspect-oriented design. Such concerns may not exist from the beginning, but emerge over ti...
Silvia Breu, Thomas Zimmermann
ICCD
2008
IEEE
202views Hardware» more  ICCD 2008»
15 years 8 months ago
CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework
— Extreme scaling practices in silicon technology are quickly leading to integrated circuit components with limited reliability, where phenomena such as early-transistor failures...
Andrea Pellegrini, Kypros Constantinides, Dan Zhan...
ICCAD
2001
IEEE
217views Hardware» more  ICCAD 2001»
15 years 8 months ago
ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Analog Circuits
: This paper describes ASF, a novel cell-level analog synthesis framework that can size and bias a given circuit topology subject to a set of performance objectives and a manufactu...
Michael Krasnicki, Rodney Phelps, James R. Hellums...