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» Developing an Open Architecture for Performance Data Mining
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ICS
2009
Tsinghua U.
15 years 8 months ago
Parametric multi-level tiling of imperfectly nested loops
Tiling is a crucial loop transformation for generating high performance code on modern architectures. Efficient generation of multilevel tiled code is essential for maximizing da...
Albert Hartono, Muthu Manikandan Baskaran, C&eacut...
99
Voted
ICMCS
2005
IEEE
116views Multimedia» more  ICMCS 2005»
15 years 7 months ago
Lossless image compression with tree coding of magnitude levels
With the rapid development of digital technology in consumer electronics, the demand to preserve raw image data for further editing or repeated compression is increasing. Traditio...
Hua Cai, Jiang Li
FPGA
2003
ACM
161views FPGA» more  FPGA 2003»
15 years 7 months ago
Implementation of BEE: a real-time large-scale hardware emulation engine
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, R...
95
Voted
HICSS
1998
IEEE
176views Biometrics» more  HICSS 1998»
15 years 6 months ago
Intelligent System for Reading Handwriting on Forms
The National Institute of Standards and Technology (NIST) has developed a form-based handprint recognition system for reading information written on forms. This public domain soft...
Michael D. Garris
IRREGULAR
1998
Springer
15 years 6 months ago
Modeling Dynamic Load Balancing in Molecular Dynamics to Achieve Scalable Parallel Execution
To achieve scalable parallel performance in Molecular Dynamics Simulation, we have modeled and implemented several dynamic spatial domain decomposition algorithms. The modeling is ...
Lars S. Nyland, Jan Prins, Ru Huai Yun, Jan Herman...