96 search results - page 11 / 20 » Device and architecture co-optimization for FPGA power reduc... |
75
Voted
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
—Interconnect structures significantly contribute to the delay, power consumption, and silicon area of modern reconfigurable architectures. The demand for higher clock frequencie...
FCCM
2008
IEEE
14 years 9 months ago
2008
IEEE
Communications infrastructure for modular reconfiguration of FPGAs needs to support the changing communications interfaces of a sequence of modules. In order to avoid the overhead...
DATE
2007
IEEE
15 years 3 months ago
2007
IEEE
Researchers previously proposed warp processors, a novel architecture capable of transparently optimizing an executing application by dynamically re-implementing critical kernels ...
FCCM
1998
IEEE
15 years 1 months ago
1998
IEEE
One of the major overheads in reconfigurable computing is the time it takes to reconfigure the devices in the system. This overhead limits the speedups possible in this exciting n...
85
Voted
VLSISP
2008
14 years 7 months ago
2008
In this paper, we introduce a new method for watermarking of IP cores for FPGA architectures where the signature (watermark) is detected at the power supply pins of the FPGA. This ...