96 search results - page 12 / 20 » Device and architecture co-optimization for FPGA power reduc... |
ICCAD
2006
IEEE
15 years 6 months ago
2006
IEEE
This work describes a new mapping technique, RAM-MAP, that identifies parts of circuits that can be efficiently mapped into the synchronous embedded memories found on field prog...
76
Voted
FPGA
2006
ACM
15 years 1 months ago
2006
ACM
The performance benefits of a monolithically stacked 3DFPGA, whereby the programming overhead of an FPGA is stacked on top of a standard CMOS layer containing the logic blocks and...
FPGA
2006
ACM
15 years 1 months ago
2006
ACM
The development of Reed-Solomon (RS) codes has allowed for improved data transmission over a variety of communication media. Although Reed-Solomon decoding provides a powerful def...
88
Voted
GLVLSI
2000
IEEE
15 years 1 months ago
2000
IEEE
A new ADC architecture is devised. This architecture is memory based, in which the last sample is used to predict the current one, resulting in both power dissipation and energy r...
FCCM
2003
IEEE
15 years 2 months ago
2003
IEEE
Although domain-specialized FPGAs can offer significant area, speed and power improvements over conventional reconfigurable devices, there are several unique and unexplored design...