96 search results - page 13 / 20 » Device and architecture co-optimization for FPGA power reduc... |
AHS
2007
IEEE
14 years 9 months ago
2007
IEEE
Online incremental evolution for a complex high-speed pattern recognition architecture has been implemented on a Xilinx Virtex-II Pro FPGA. The fitness evaluation module is entir...
FPGA
2005
ACM
15 years 3 months ago
2005
ACM
This paper describes the Altera Stratix II™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be p...
ASAP
2009
IEEE
15 years 6 months ago
2009
IEEE
The advent of the mobile age has heavily changed the requirements of today’s communication devices. Data transmission over interference-prone wireless channels requires addition...
ISLPED
2010
ACM
14 years 9 months ago
2010
ACM
Structured ASICs provide an exciting middle ground between FPGA and ASIC design methodologies. Compared to ASIC, structured ASIC based designs require lower non recurring engineer...
ISCAS
2007
IEEE
15 years 3 months ago
2007
IEEE
— This paper describes the hardware architecture for a flexible probability density estimation unit to be used in a Large Vocabulary Speech Recognition System, and targeted for m...