96 search results - page 14 / 20 » Device and architecture co-optimization for FPGA power reduc... |
ICCD
2008
IEEE
15 years 3 months ago
2008
IEEE
— SRAMs typically represent half of the area and more than half of the transistors on a chip today. Variability increases as feature size decreases, and the impact of variability...
ICCD
2007
IEEE
15 years 6 months ago
2007
IEEE
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
TVLSI
2010
14 years 4 months ago
2010
In many applications, a reduction of the amount of the original data or a representation of the original data by a small set of variables is often required. Among many techniques, ...
TVLSI
2010
14 years 4 months ago
2010
Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise mar...
DAC
1999
ACM
15 years 10 months ago
1999
ACM
The advent of portable and high-density devices has made power consumption a critical design concern. In this paper, we address the problem of reducing power consumption via gate-...