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GLVLSI
2010
IEEE
136views VLSI» more  GLVLSI 2010»
15 years 2 months ago
Thermal-aware compilation for system-on-chip processing architectures
The development of compiler-based mechanisms to reduce the percentage of hotspots and optimize the thermal profile of large register files has become an important issue. Thermal...
Mohamed M. Sabry, José L. Ayala, David Atie...
DAC
2009
ACM
15 years 10 months ago
O-Router:an optical routing framework for low power on-chip silicon nano-photonic integration
In this work, we present a new optical routing framework, O-Router for future low-power on-chip optical interconnect integration utilizing silicon compatible nano-photonic devices...
Duo Ding, Yilin Zhang, Haiyu Huang, Ray T. Chen, D...
JCP
2008
118views more  JCP 2008»
14 years 9 months ago
Power-efficient Instruction Encoding Optimization for Various Architecture Classes
A huge application domain, in particular, wireless and handheld devices strongly requires flexible and powerefficient hardware with high performance. This can only be achieved with...
Diandian Zhang, Anupam Chattopadhyay, David Kammle...
FPL
2005
Springer
125views Hardware» more  FPL 2005»
15 years 2 months ago
Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor
This paper describes novel data-path architecture for FPGA-based multimedia processors. The proposed circuit can adapt itself at run-time to different operations and data wordleng...
Marco Lanuzza, Stefania Perri, Martin Margala, Pas...
CODES
2010
IEEE
14 years 7 months ago
A greedy buffer allocation algorithm for power-aware communication in body sensor networks
Monitoring human movements using wireless sensory devices promises to revolutionize the delivery of healthcare services. In spite of their potentials for many application domains,...
Hassan Ghasemzadeh, Roozbeh Jafari