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DATE
2007
IEEE
150views Hardware» more  DATE 2007»
15 years 3 months ago
A low-SER efficient core processor architecture for future technologies
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
IPPS
2006
IEEE
15 years 3 months ago
Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs
The development of Field Programmable Gate Arrays (FPGAs) had tremendous improvements in the last few years. They were extended from simple logic circuits to complex Systems-on-Ch...
Michael Hübner, Christian Schuck, Jürgen...
IPPS
2006
IEEE
15 years 3 months ago
An adaptive system-on-chip for network applications
This paper presents the hardware architecture of DynaCORE, a dynamically reconfigurable system-on-chip for network applications. DynaCORE is an application specific coprocessor ...
Roman Koch, Thilo Pionteck, Carsten Albrecht, Erik...
VLSID
2002
IEEE
90views VLSI» more  VLSID 2002»
15 years 9 months ago
Software-Only Bus Encoding Techniques for an Embedded System
Microprocessors with built-in Liquid Crystal Device (LCD) controllers and equipped with Flash ROM are common in mobile computing applications. In the first part of the paper, a so...
Wei-Chung Cheng, Jian-Lin Liang, Massoud Pedram
DAC
2006
ACM
15 years 10 months ago
Gate sizing: finFETs vs 32nm bulk MOSFETs
FinFET devices promise to replace traditional MOSFETs because of superior ability in controlling leakage and minimizing short channel effects while delivering a strong drive curre...
Brian Swahn, Soha Hassoun