96 search results - page 4 / 20 » Device and architecture co-optimization for FPGA power reduc... |
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Voted
ASPDAC
2005
ACM
14 years 11 months ago
2005
ACM
- The use of synthesizable reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such domain-special cores are being used for their flexibility, po...
TCAD
2010
14 years 4 months ago
2010
Abstract--This paper presents a technology mapping algorithm for field-programmable gate array architectures with dual supply voltages (Vdds) for power optimization. This is done w...
ICMCS
2005
IEEE
15 years 3 months ago
2005
IEEE
The paper presents a high-performance architecture of the bit-plane coder for the embedded block coding algorithm in JPEG 2000. The architecture adopts a pipeline structure and is...
FPL
2007
Springer
15 years 3 months ago
2007
Springer
This paper presents a novel architecture for domain-specific FPGA devices. This architecture can be optimised for both speed and density by exploiting domain-specific informatio...
FPL
2004
Springer
15 years 2 months ago
2004
Springer
This paper investigates experimentally the quantitative impact of pipelining on energy per operation for two representative FPGA devices: a 0.13µm CMOS high density/high speed FPG...