96 search results - page 5 / 20 » Device and architecture co-optimization for FPGA power reduc... |
121
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FPGA
1999
ACM
15 years 1 months ago
1999
ACM
Pipelining of data path structures increases the throughput rate at the expense of enlarged resource usage and latency unless architectures optimized towards specific applications...
134
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FPGA
2006
ACM
15 years 1 months ago
2006
ACM
In this paper, we propose a technique to flexibly implement genetic algorithms for various problems on FPGAs. For the purpose, we propose a basic architecture for GA which consist...
DATE
2010
IEEE
15 years 2 months ago
2010
IEEE
— The paper introduces novel field programmable gate array (FPGA) circuits based on hybrid CMOS/resistive switching device (memristor) technology and explores several logic archi...
NOCS
2007
IEEE
15 years 3 months ago
2007
IEEE
In this paper we present a new clustered mesh FPGA architecture where each cluster local interconnect is implemented as an MFPGA tree network [6]. Unlike previous clustered mesh a...
ICCD
2004
IEEE
15 years 6 months ago
2004
IEEE
A negative effect of ever-shrinking supply and threshold voltages is the larger percentage of total power consumption that comes from leakage current. Several techniques have been...