96 search results - page 9 / 20 » Device and architecture co-optimization for FPGA power reduc... |
VLSID
2007
IEEE
15 years 9 months ago
2007
IEEE
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
DATE
2004
IEEE
15 years 1 months ago
2004
IEEE
Mobile video processing as defined in standards like MPEG-4 and H.263 contains a number of timeconsuming computations that cannot be efficiently executed on current hardware archi...
ISCA
2005
IEEE
15 years 3 months ago
2005
IEEE
Recent years have seen a burgeoning interest in embedded wireless sensor networks with applications ranging from habitat monitoring to medical applications. Wireless sensor networ...
91
Voted
JSA
2010
14 years 4 months ago
2010
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
76
Voted
ERSA
2008
14 years 11 months ago
2008
Partial reconfiguration (PR) reveals many opportunities for integration into FPGA design for potential system optimizations such as reduced area, increased performance, and increa...