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» Diagonal routing in high performance microprocessor design
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72
Voted
MTV
2007
IEEE
121views Hardware» more  MTV 2007»
15 years 3 months ago
Chico: An On-chip Hardware Checker for Pipeline Control Logic
The widening gap between CPU complexity and verification capability is becoming increasingly more salient. It is impossible to completely verify the functionality of a modern mic...
Andrew DeOrio, Adam Bauserman, Valeria Bertacco
MINENET
2005
ACM
15 years 3 months ago
A first step toward understanding inter-domain routing dynamics
BGP updates are triggered by a variety of events such as link failures, resets, routers crashing, configuration changes, and so on. Making sense of these updates and identifying ...
Kuai Xu, Jaideep Chandrashekar, Zhi-Li Zhang
WINET
2008
77views more  WINET 2008»
14 years 9 months ago
VE-mobicast: a variant-egg-based mobicast routing protocol for sensornets
In this paper, we present a new "spatiotemporal multicast", called a "mobicast", protocol for supporting applications which require spatiotemporal coordination...
Yuh-Shyan Chen, Shin-Yi Ann, Yun-Wei Lin
96
Voted
INFOCOM
2005
IEEE
15 years 3 months ago
IPStash: a set-associative memory approach for efficient IP-lookup
—IP-Lookup is a challenging problem because of the increasing routing table sizes, increased traffic, and higher speed links. These characteristics lead to the prevalence of hard...
Stefanos Kaxiras, Georgios Keramidas
91
Voted
MICRO
1994
IEEE
123views Hardware» more  MICRO 1994»
15 years 1 months ago
The effects of predicated execution on branch prediction
High performance architectures have always had to deal with the performance-limiting impact of branch operations. Microprocessor designs are going to have to deal with this proble...
Gary S. Tyson