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STTT
2011
195views more  STTT 2011»
14 years 4 months ago
Parallel probabilistic model checking on general purpose graphics processors
We present algorithms for parallel probabilistic model checking on general purpose graphic processing units (GPGPUs). Our improvements target the numerical components of the tradit...
Dragan Bosnacki, Stefan Edelkamp, Damian Sulewski,...
ICCD
2006
IEEE
137views Hardware» more  ICCD 2006»
15 years 6 months ago
Implementation and Evaluation of On-Chip Network Architectures
— Driven by the need for higher bandwidth and complexity reduction, off-chip interconnect has evolved from proprietary busses to networked architectures. A similar evolution is o...
Paul Gratz, Changkyu Kim, Robert G. McDonald, Step...
ICDCS
1997
IEEE
15 years 1 months ago
Evaluating CORBA Latency and Scalability Over High-Speed ATM Networks
Conventional implementations of CORBA communication middleware incur significant overhead when used for performance-sensitive applications over high-speed networks. As gigabit ne...
Douglas C. Schmidt, Aniruddha S. Gokhale
HCW
1998
IEEE
15 years 1 months ago
Implementing Distributed Synthetic Forces Simulations in Metacomputing Environments
A distributed, parallel implementation of the widely used Modular Semi-Automated Forces ModSAF Distributed Interactive Simulation DIS is presented, with Scalable Parallel Processo...
Sharon Brunett, Dan Davis, Thomas Gottschalk, Paul...
ICC
2009
IEEE
116views Communications» more  ICC 2009»
14 years 7 months ago
Efficient Implementation of Binary Sequence Generator for WiMAX and WRAN on Programmable Digital Signal Processor
In this paper, an efficient design for implementing binary sequence generator on 32-bit instruction execution mode TI TMS320C6416 DSP is presented. The main goal is to achieve high...
Lok Tiing Tie, Ser Wah Oh, K. J. M. Kua