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CIBB
2009
15 years 6 months ago
On the Use of Temporal Formal Logic to Model Gene Regulatory Networks
Modelling activities in molecular biology face the difficulty of prediction to link molecular knowledge with cell phenotypes. Even when the interaction graph between molecules is k...
Gilles Bernot, Jean-Paul Comet
147
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PATMOS
2005
Springer
15 years 11 months ago
Design of Variable Input Delay Gates for Low Dynamic Power Circuits
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
TVLSI
2008
111views more  TVLSI 2008»
15 years 5 months ago
GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering
This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding program...
Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wil...
SIAMCO
2008
113views more  SIAMCO 2008»
15 years 5 months ago
Singularly Perturbed Piecewise Deterministic Games
Abstract. In this paper we consider a class of hybrid stochastic games with the piecewise openloop information structure. These games are indexed over a parameter which represents...
Alain Haurie, Francesco Moresino
IM
2007
15 years 5 months ago
A Service Middleware that Scales in System Size and Applications
We present a peer-to-peer service management middleware that dynamically allocates system resources to a large set of applications. The system achieves scalability in number of no...
Constantin Adam, Rolf Stadler, Chunqiang Tang, Mal...