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ARITH
2007
IEEE
15 years 4 months ago
A New Family of High.Performance Parallel Decimal Multipliers
This paper introduces two novel architectures for parallel decimal multipliers. Our multipliers are based on a new algorithm for decimal carry–save multioperand addition that us...
Álvaro Vázquez, Elisardo Antelo, Pao...
ARITH
2005
IEEE
15 years 3 months ago
Low Latency Pipelined Circular CORDIC
The pipelined CORDIC with linear approximation to rotation has been proposed to achieve reductions in delay, power and area; however, the schemes for rotation (multiplication) and...
Elisardo Antelo, Julio Villalba
HOTI
2008
IEEE
15 years 4 months ago
High-Speed, Short-Latency Multipath Ethernet Transport for Interconnections
In this paper, we propose an Ethernet-based transmission-guaranteed, congestion-controlled network using a simplified multi-path aggregation scheme. Multi-path aggregation increas...
Nobuyuki Enomoto, Hideyuki Shimonishi, Junichi Hig...
ASAP
2003
IEEE
155views Hardware» more  ASAP 2003»
15 years 2 months ago
Decimal Multiplication Via Carry-Save Addition
Decimal multiplication is important in many commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. This p...
Mark A. Erle, Michael J. Schulte
ISHPC
2003
Springer
15 years 2 months ago
Improving Memory Latency Aware Fetch Policies for SMT Processors
Abstract. In SMT processors several threads run simultaneously to increase available ILP, sharing but competing for resources. The instruction fetch policy plays a key role, determ...
Francisco J. Cazorla, Enrique Fernández, Al...