787 search results - page 23 / 158 » Digital Algebra and Circuits |
88
Voted
ISCAS
1995
IEEE
15 years 4 months ago
1995
IEEE
— This paper introduces a simple analytical model for estimating standby and switching power dissipation in deep submicron CMOS digital circuits. The model is based on Berkeley S...
87
Voted
DSD
2010
IEEE
15 years 18 days ago
2010
IEEE
—This paper presents an approximate Maximum Common Subgraph (MCS) algorithm, specifically for directed, cyclic graphs representing digital circuits. Because of the application d...
92
Voted
DAC
1994
ACM
15 years 4 months ago
1994
ACM
Higher levels of integration have led to a generation of integrated circuits for which power dissipation and reliability are major design concerns. In CMOS circuits, both of these ...
107
Voted
TCAD
2002
15 years 1 days ago
2002
Abstract--This paper investigates the application of simultaneous retiming and clock scheduling for optimizing synchronous circuits under setup and hold constraints. Two optimizati...
JSA
2006
15 years 10 days ago
2006
A NULL Cycle Reduction (NCR) technique is developed to increase the throughput of NULL Convention Logic systems, by reducing the time required to flush complete DATA wavefronts, c...