47 search results - page 3 / 10 » Digital Circuit Verification Using Partially-Ordered State M... |
FDL
2006
IEEE
13 years 10 months ago
2006
IEEE
In this work, an approach to the `verification-oriented' modeling of the analog parts' behavior of mixed-signal circuits is presented. Starting from a continuous-time, c...
DATE
2000
IEEE
13 years 10 months ago
2000
IEEE
Clock and data recovery circuits are essential components in communication systems. They directly influence the bit-error-rate performance of communication links. It is desirable...
DAC
2009
ACM
14 years 7 months ago
2009
ACM
Continuously shrinking feature sizes result in an increasing susceptibility of circuits to transient faults, e.g. due to environmental radiation. Approaches to implement fault tol...
DSD
2008
IEEE
14 years 22 days ago
2008
IEEE
Testability is one of the most important factors that are considered during design cycle along with reliability, speed, power consumption, cost and other factors important for a c...
EURODAC
1994
IEEE
13 years 10 months ago
1994
IEEE
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...