47 search results - page 6 / 10 » Digital Circuit Verification Using Partially-Ordered State M... |
CASES
2006
ACM
15 years 3 months ago
2006
ACM
Designers of SoCs with non-digital components, such as analog or MEMS devices, can currently use high-level system design languages, such as SystemC, to model only the digital par...
ICSE
2010
IEEE-ACM
14 years 11 months ago
2010
IEEE-ACM
Typestate analysis determines whether a program violates a set of finite-state properties. Because the typestate-analysis problem is statically undecidable, researchers have propo...
CIIA
2009
14 years 10 months ago
2009
Abstract. Formal verification of digital systems is achieved, today, using one of two main approaches: states exploration (mainly model checking and equivalence checking) or deduct...
89
Voted
EMSOFT
2006
Springer
15 years 1 months ago
2006
Springer
We report on a case study in which the model checker Uppaal is used to formally model parts of Zeroconf, a protocol for dynamic configuration of IPv4 link-local addresses that has...
DAC
2003
ACM
15 years 10 months ago
2003
ACM
We present an algorithm that checks behavioral consistency between an ANSI-C program and a circuit given in Verilog using Bounded Model Checking. Both the circuit and the program ...