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LCTRTS
2007
Springer
15 years 4 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
EMSOFT
2004
Springer
15 years 3 months ago
Binary translation to improve energy efficiency through post-pass register re-allocation
Energy efficiency is rapidly becoming a first class optimization parameter for modern systems. Caches are critical to the overall performance and thus, modern processors (both hig...
Kun Zhang, Tao Zhang, Santosh Pande
VLDB
1995
ACM
97views Database» more  VLDB 1995»
15 years 1 months ago
Processing Object-Oriented Queries with Invertible Late Bound Functions
New demandsare put on query processing in Object-Oriented(00) databasesto provide efficient andrelationally completequery languages. A flexible 00 data model requires overloading ...
Staffan Flodin, Tore Risch
FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
14 years 10 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
SECON
2010
IEEE
14 years 8 months ago
Adaptive Instantiation of the Protocol Interference Model in Mission-Critical Wireless Networks
Interference model is the basis of MAC protocol design in wireless networks, and it directly affects the efficiency and predictability of wireless messaging. To exploit the strengt...
Xin Che, Xiaohui Liu, Xi Ju, Hongwei Zhang