1653 search results - page 113 / 331 » Directed tree-width examples |
DATE
2000
IEEE
15 years 6 months ago
2000
IEEE
This paper is about gate sizing under a statistical delay model. It shows we can solve the gate sizing problem exactly for a given statistical delay model. The formulation used al...
ICRA
2000
IEEE
15 years 6 months ago
2000
IEEE
We describe in this paper potential problems that may appear in image-based visual servoing when the initial camera position is far away from its desired position. We show by conc...
102
click to vote
DAC
1999
ACM
15 years 6 months ago
1999
ACM
As interconnect feature sizes continue to scale to smaller dimensions, long interconnect can dominate the IC timing performance, but the interconnect parameter variations make it ...
105
click to vote
DAC
1999
ACM
15 years 6 months ago
1999
ACM
The purpose of this paper is to develop a exible design for test methodology for testing a core-based system on chip SOC . The novel feature of the approach is the use an embedde...
113
click to vote
DATE
1999
IEEE
15 years 6 months ago
1999
IEEE
Commonly used scheduling algorithms in high-level synthesis only accept one process at a time and are not capable of sharing resources across process boundaries. This results in t...